Stacked gate-all-around nanosheet transistors with full-air-spacers for reducing parasitic capacitance to improve device and circuit performance

Abstract

In this paper, we propose a full-air-spacers (FAS, air spacers and air inner spacers) technique and a feasible fabrication approach on gate all around (GAA) nanosheet field-effect-transistors (NSFETs) by a backside selective etching (BSE). Compared with NSFETs with SiN_x spacers and low-κ spacers, the FAS NSFETs exhibit no obvious degradation in DC characteristics, but show enormous improvements in AC characteristics and circuit benefits. The FAS technology provides 79.40 % reduction in effective capacitance and 75.71 % reduction in intrinsic delay. Moreover, the power consumption is reduced by 60.84 % at the same frequency, while the frequency gain is increased by 87.50 % at the same power consumption on the 17-stage ring oscillators (ROs). In addition, the FAS NSFETs-based 6T static random memories (SRAMs) cell has achieved 44.26 % and 82.46 % decrease in read time and write time, while 8.40 % and 4.54 % improvement in read noise tolerance and write noise tolerance, compared to the SiN_x-NSFETs-based 6T-SRAM cell.