First demonstration of monolithic CMOS based on 4-inch three-layer MoTe2

Abstract

In recent years, two-dimensional (2D) semiconductors, which possess atomic-scale thickness and superior electrostatic control, have been identified as the most promising channel material candidates for sub-1 nm technology nodes. Most researches on 2D materials complementary metal oxide semiconductors (2D CMOS) have encountered several challenges, including the lack of effective doping approaches and incompatibility with Si-CMOS processes, which have hindered the further development of 2D semiconductor-based integrated circuits (2D-ICs). Here, we present the fabrication of 4-inch wafer-scale MoTe₂ CMOS inverter arrays, based on a top-gate transistor architecture for MoTe₂ film with three-layer thickness. Following the co-optimization of contact and top-gate processes, the MoTe₂ CMOS exhibited a voltage gain of approximately 35. This work demonstrates the feasibility of fabricating wafer-scale CMOS 2D-ICs.