A novel 4H–SiC power MOSFET with source-side poly-Si/SiC heterojunctions for single-event effects hardening

Abstract

—A novel SiC power MOSFET structure with Source-side Poly-Si/SiC Heterojunctions (SH-MOS) is proposed by introducing Poly-Si regions of the device's source side. Introducing a P + Poly-Si region at the center of the device helps discharge holes, thereby reducing the accumulation of holes beneath the gate oxide layer caused by heavy ion impacts and improving resistance to single-event gate rupture (SEGR). Besides, The P + Poly-Si and N SiC form a p/n type Poly-Si/SiC heterojunction diode (HJD), effectively improving the device's reverse conduction and recovery performance. In addition, introducing a N + Poly-Si region to replace original N + SiC source region on the source side. Due to the different energy bands of the n/p type Poly-Si/SiC heterojunction, the hole current of parasitic BJT’ emitter increases during the single event irradiation process of SH-MOS. This results in a significant decrease in the current gain of the parasitic BJT, thereby improving its Single Event Burnout (SEB) performance. Simulation results show that under the same irradiation conditions, SH-MOS exhibits superior SEGR and SEB resistance compared to Con-MOS. The SEB threshold voltage of SH-MOS is 660 V, which is 214.29 % higher than the 210 V of the original N + SiC source region MOSFET. In addition, the novel SH-MOS structure reduces VF by 45.36 % and reverse recovery charge (Qrr) by 33.32 % compared to Con-MOS, without causing any significant degradation in forward conduction or blocking characteristics.