Borophene vertical dopingless Tunnel FET with high-κ dielectric and incorporating gate–drain underlapping technique

Abstract

Tunnel-FETs are ideal for low-power electronic applications, particularly in areas requiring steep subthreshold slope and energy-efficient switching. However, traditional TFETs face major issues, including low ON-current ($I_{\text{ON}}$), random dopant fluctuations, and ambipolar conduction, which limit their performance and scalability. To address these issues, this study proposes the novel design of a borophene-based vertical dopingless TFET, incorporating a gate–drain underlapping (GDU) technique. The study employs high-$\kappa$ dielectrics, specifically ${\text{HfO}}_2$, to improve electrostatic control within the device. Through extensive analysis and optimisation, the proposed device, featuring a 1nm ${\text{HfO}}_2$ dielectric, achieves a remarkable subthreshold swing of 8.44mV/dec and an impressive $I_{\text{ON}}$ of 2.45$\times$10^-4 A/$\mu$m at a drain bias of 0.5V. The GDU technique effectively suppresses ambipolar conduction and reduces gate-to-drain capacitance, significantly improving device performance. By leveraging borophene’s unique properties and the novel vertical dopingless architecture, this work advances the design of TFETs.