{"title":"A high isolation 16–19 GHz down-conversion mixer in 0.18-μm SiGe Bi-CMOS","authors":"Jun-Da Chen, Shan-Yi Cheng","doi":"10.1016/j.vlsi.2025.102358","DOIUrl":null,"url":null,"abstract":"<div><div>This paper introduces a novel down-conversion mixer chip explicitly designed for low-orbit satellites operating in the K-band frequency range (16–19 GHz). The chip, fabricated using TSMC's 0.18-μm SiGe Bi-CMOS technology, offers a unique combination of MOS and HBT bipolar junction transistors (BJTs). The double-balanced mixer uses Marchand baluns on the RF and LO ports to convert single-ended signals to differential ones. Transformer coupling between the RF transconductance and LO switching stages ensures excellent isolation and linearity. The proposed series-parallel switching stage effectively increases the switching current at frequencies above 10 GHz and improves the conversion gain at low voltages. The measured results for the proposed mixer demonstrate a power conversion gain of 3.4–4.7 dB with a flat variation of ±0.7 dB and an input third-order intercept point (IIP3) ranging from −1.8 to 0 dBm. These results indicate the performance of the mixer in terms of power gain and linearity. The isolation of RF-to-LO, RF-to-IF, and LO-to-IF are 60, 62, and 30 dB at 19 GHz, respectively, which is crucial for preventing signal interference. The total DC power consumption for 1.1/1 V dual voltage with output buffer is 16.6 mW. The total chip size is 1.11 × 0.843 mm<sup>2</sup>.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"102 ","pages":"Article 102358"},"PeriodicalIF":2.2000,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S016792602500015X","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This paper introduces a novel down-conversion mixer chip explicitly designed for low-orbit satellites operating in the K-band frequency range (16–19 GHz). The chip, fabricated using TSMC's 0.18-μm SiGe Bi-CMOS technology, offers a unique combination of MOS and HBT bipolar junction transistors (BJTs). The double-balanced mixer uses Marchand baluns on the RF and LO ports to convert single-ended signals to differential ones. Transformer coupling between the RF transconductance and LO switching stages ensures excellent isolation and linearity. The proposed series-parallel switching stage effectively increases the switching current at frequencies above 10 GHz and improves the conversion gain at low voltages. The measured results for the proposed mixer demonstrate a power conversion gain of 3.4–4.7 dB with a flat variation of ±0.7 dB and an input third-order intercept point (IIP3) ranging from −1.8 to 0 dBm. These results indicate the performance of the mixer in terms of power gain and linearity. The isolation of RF-to-LO, RF-to-IF, and LO-to-IF are 60, 62, and 30 dB at 19 GHz, respectively, which is crucial for preventing signal interference. The total DC power consumption for 1.1/1 V dual voltage with output buffer is 16.6 mW. The total chip size is 1.11 × 0.843 mm2.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.