All pass transformation based variable digital filter design using low power approximate floating point adder and low power compressor based approximate multiplier

Abstract

Digital signal processing filters are essential in various applications that require a balance between accuracy, power efficiency, and computational complexity. Variable digital filters (VDF) are increasingly important in signal processing and communication. This manuscript proposes All Pass Transformation dependent Variable Digital Filter using Low Power Approximate Floating Point Adder and Low Power Compressor based Approximate Multiplier (APT-VDF-LP-AFPA-LP-CAM). The proposed APT-VDF-LP-AFPA-LP-CAM overcomes performance limitations by utilizing advanced approximation techniques to enhance speed and reduce power consumption. The LP-AFPA leverages state-of-the-art approximate compound gates to accelerate addition and minimize carry propagation delays, while the LP-CAM employs a divide and conquer method for efficient partial product generation. The proposed approach is simulated using Xilinx ISE 14.5, shows significant improvements with 20.98 %, 12.67 % and 33.76 % reduction in delay and 21.90 %, 31.45 % and 27.45 % decrease in power consumption, and an operating frequency of 210.87 MHz. These advancements outperform existing methods, such as APT-VDF utilizing ternary adder and multiplier (APT-VDF-TA-TM), All-pass digital filters with dual carry select adder (CDF-ESDCSA-TRAF), Power-efficient FIR filters with ESSA and VL-CSKA (ESSA-VL-CSKA). This work underscores the effectiveness of integrating advanced approximation techniques in APT-VDF design, paving the way for future developments in high-speed and low-power digital signal processing applications.