An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process

IF 2.2 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Chua-Chin Wang , Pradyumna Vellanki , Shih-Heng Luo , Ralph Gerard B. Sangalang
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引用次数: 0

Abstract

This investigation demonstrates an on-chip temperature sensor with a maximum linear error less than 0.4% and 0.5 °C resolution. The design comprises Current-to-Frequency Converters (CFC), complementary (CTAT), and proportional (PTAT) to absolute temperature current generator circuits. Most important of all, the proposed sensor is featured with the ratio of these two currents to enhance the linearity and high resolution. The proposed sensor was realized using a 180-nm CMOS process. The core area is 0.196 mm2. The measurement results show 0.3484% maximum linearity error for the PTAT/CTAT ratio. The maximum output frequency of the temperature detector is 4.817 MHz, with the highest power consumption of 20.13 mW. It was proved to be used in a –40 °C100 °C temperature detection range with 0.5 °C resolution.

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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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