Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA

Abstract

Physical unclonable functions (PUF) are a type of physical system that harvests data from integrated circuits fragile physical components. These systems offer a highly secure way to generate cryptographic keys for cryptographic operations and protect secure IPs from threats, manipulation, and duplication due to their un-clonability properties. Prior literature has designed various Arbiter PUFs with 2:1 MUX, but they consume a large area to generate the larger response bits. Based on our literature survey, this is the first paper to design an Arbiter PUF with 4:1 MUX, which reduces the area overhead. This paper utilizes a 4:1MUX APUF design is implemented on 10 ZYNQ-7000 SoC FPGA devices using the LUT6 primitive to overcome the challenge of designing an unbiased PUF architecture on the FPGA device. The study also presents two different methodologies to generate responses for the corresponding challenge of 4:1 MUX Arbiter PUF. The design showed a uniqueness rate of 49 % when evaluated on both methodologies. The dependability percentages for temperature fluctuations (20–70 °C) were 99 %. Finally, the performance parameter of the proposed PUF is state-of-the-art.