Runlian Zhang , Yu Mo , Zhaoxuan Pan , Hailong Zhang , Yongzhuang Wei , Xiaonian Wu
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引用次数: 0
Abstract
CutMix data augmentation can provide a large amount of augmented data for DL-SCA (deep learning side channel attacks) by generating new power traces. However, traces generated by CutMix may lose dependency with the new label, which may reduce the accuracy of the training model. In light of this, we propose an improved intra-class CutMix data augmentation method. Firstly, the original traces are classified by the label. Then, the original traces are selected by the same label constraint to generate new traces according to CutMix, which can ensure the dependency between the generated trace and its label. Furthermore, in order to maintain balance among different classified datasets, the traces are generated sequentially according to distinct labels. Finally, based on the augmented traces, the Multilayer Perceptron (MLP) and Convolutional Neural Network (CNN) models can be constructed and trained to recover the key of AES. In order to verify the effectiveness of the proposed method, we conduct experimental evaluations using the MLP and CNN models based on DPA-contest v4 dataset and ASCAD dataset. The test results show that the traces generated with the intra-class CutMix method can be very similar to the original traces, and the MLP and CNN models can be effectively trained based on the generated traces to recover the key of AES. Besides, compared with existing data augmentation methods, the proposed method can complete secret key recovery with faster convergence and fewer traces.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.