Third-order resonance networks and their application to chaos generation

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-01-25 DOI:10.1016/j.vlsi.2025.102348

Ahmed S. Elwakil , Brent J. Maundy , Costas Psychalinos , Amr Elsonbaty

引用次数: 0

Abstract

In this work, we re-visit third-order RLC resonance networks depicting the set of four basic series and parallel resonance circuits where two circuits are admittance based (parallel resonance) and the other two are impedance-based (series resonance). We show that all circuits exhibit resonance at a single frequency and derive its expression. However, all circuits also have another below-resonance or above-resonance critical frequency at which the input impedance (or admittance) is zero. We call this frequency, the dip-frequency and a change in phase also occurs at this frequency. Therefore, the third-order resonance networks exhibit two phase changes: one at the resonance frequency and another at the dip frequency. An application in realizing third-order non-autonomous chaotic oscillators is described and experimental results are provided.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.