Youngwoo Jeong, Joungmin Park, Raehyeong Kim, Seung Eun Lee
{"title":"SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources","authors":"Youngwoo Jeong, Joungmin Park, Raehyeong Kim, Seung Eun Lee","doi":"10.1016/j.vlsi.2024.102337","DOIUrl":null,"url":null,"abstract":"<div><div>Approximate computing constitutes a paradigm in which accuracy is exchanged for enhanced energy efficiency when contrasted with conventional computing methodologies. This approach has been devised to address the escalating demand stemming from the rapid expansion of application systems. This paper proposes an approximate multiplier for systems with heavy computational load. By amalgamating the attributes of a Dynamic range unbiased multiplier (DRUM) with an Approximate wallace tree multiplier (AWTM), we have devised a Synergetic energy-efficient approximate multiplier (SEAM) aimed at mitigating the occurrence of worst-case errors inherent in AWTM. The SEAM was analyzed for circuit area and power consumption using Design Compiler with Synopsys GPDK 32 nm. Experimental results demonstrated that SEAM achieved up to 80.46% reduction in circuit area and 82.6% reduction in power consumption compared to a precise multiplier. Furthermore, compared to DRUM, SEAM showed a 15.55% reduction in circuit area and 45.73% reduction in power consumption. In order to validate the feasibility of the proposed approximate multiplier, the circuit was implemented on a Field-programmable gate array (FPGA) and applied to a fuzzy logic-based pathfinding algorithm and a Convolutional neural network (CNN) accelerator. For the pathfinding algorithm, most error metrics of the SEAM showed similar values to the DRUM. Moreover, when applied to the CNN accelerator and experimented with the CIFAR-10 dataset and MNIST dataset, the proposed multiplier exhibited identical precision, recall, and F1 score values. Despite applying SEAM, we achieved a maximum 3.1% increase in classification metrics for a specific case. These results indicate the significant potential of the SEAM in reducing the area of overall system while minimizing errors.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"101 ","pages":"Article 102337"},"PeriodicalIF":2.2000,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926024002013","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
Approximate computing constitutes a paradigm in which accuracy is exchanged for enhanced energy efficiency when contrasted with conventional computing methodologies. This approach has been devised to address the escalating demand stemming from the rapid expansion of application systems. This paper proposes an approximate multiplier for systems with heavy computational load. By amalgamating the attributes of a Dynamic range unbiased multiplier (DRUM) with an Approximate wallace tree multiplier (AWTM), we have devised a Synergetic energy-efficient approximate multiplier (SEAM) aimed at mitigating the occurrence of worst-case errors inherent in AWTM. The SEAM was analyzed for circuit area and power consumption using Design Compiler with Synopsys GPDK 32 nm. Experimental results demonstrated that SEAM achieved up to 80.46% reduction in circuit area and 82.6% reduction in power consumption compared to a precise multiplier. Furthermore, compared to DRUM, SEAM showed a 15.55% reduction in circuit area and 45.73% reduction in power consumption. In order to validate the feasibility of the proposed approximate multiplier, the circuit was implemented on a Field-programmable gate array (FPGA) and applied to a fuzzy logic-based pathfinding algorithm and a Convolutional neural network (CNN) accelerator. For the pathfinding algorithm, most error metrics of the SEAM showed similar values to the DRUM. Moreover, when applied to the CNN accelerator and experimented with the CIFAR-10 dataset and MNIST dataset, the proposed multiplier exhibited identical precision, recall, and F1 score values. Despite applying SEAM, we achieved a maximum 3.1% increase in classification metrics for a specific case. These results indicate the significant potential of the SEAM in reducing the area of overall system while minimizing errors.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.