A low-power two-step gray-code counter for single-slope ADC in CMOS image sensors

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2025-01-03 DOI:10.1016/j.vlsi.2024.102341

Xiaofeng Gu, Sikai Zhong, Xiaoyu Zhong, Taotao Zhou, Wenzhuo Li, Zhiguo Yu

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引用次数: 0

Abstract

A low-power gray-code (GC) counter is proposed for the single-slope ADC (SS-ADC) in CMOS image sensors. The counter performs the GC counting directly to halve the clock frequency of each bit and minimize the flipping bits between two neighboring numbers. The bitwise-inversion (BWI) structure is utilized in the GC counter to perform complementary operations for the digital correlated double sampling. Moreover, a two-step (TS) GC counter with in-column error calibration is proposed to further reduce the power consumption. The TS-GC counter is implemented in a 10-bit SS-ADC. Simulated results show that the GC counter reduces power consumption by over 30% compared to a BWI counter, and the TS-GC counter reduces by over 18% compared to a TS double-data-rate counter. The differential nonlinearity and integral nonlinearity of the SS-ADC with the TS-GC counter are ＋0.4/

-

0.38 LSB and ＋0.45/

-

0.97 LSB, respectively, and the effective number of bits is 9.53 bit.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.