A compact structure for triple-memristor maps with a hyperplane of fixed points

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-12-30 DOI:10.1016/j.vlsi.2024.102334

Viet-Thanh Pham , Jesus M. Munoz-Pacheco , Andrei Velichko , Salah Mahmoud Boulaaras , Shaher Momani

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引用次数: 0

Abstract

Memristor maps verified the universal usage of memristors in nonlinear maps. Although almost published works investigate chaotic maps constructing with only one memristor, maps including multiple memristors attract interest because of their flexible structures. By combining three memristors, we introduce a triple-memristor model, which is general and can be easily used to design different chaotic maps. The presence of a hyperplane of fixed points and absence of fixed point are special characteristics of such a model. For illustrating the application of such a model, a specific triple-memristor map, named TMM

_{1}

map, has been studied through both theoretical and experimental discoveries. Results indicate the chaos of TMM

_{1}

map and its feasibility. The positive results show the potential of building chaotic maps with multiple memristors.

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.