Localisation of malicious nets in integrated circuits using unsupervised methodologies

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-12-16 DOI:10.1016/j.vlsi.2024.102312

Tapobrata Dhar, Chandan Giri, Surajit Kumar Roy

引用次数: 0

Abstract

A novel golden-model free unsupervised static analysis method is proposed for detecting Hardware Trojan Horse (HTH) nets in integrated circuits (IC). Established and newly introduced gate-level HTH features are extracted and separate feature subsets are obtained pertaining to natures of combinational and sequential HTHs. Local outlier analysis is used to identify the nets that exhibit behaviours pertaining to specific HTH types. Heuristic localisation process through neighbourhood analysis is used to identify malicious nets within the gate-level netlist of the host IC. The proposed localisation technique detect HTH nets with consistent high accuracy and high average true positive rate (TPR).

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.