Sameera Shaik , S.M. Srinivasavarma Vegesna , Noor Mahammad S.K.
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引用次数: 0
Abstract
Intrusion Detection System (IDS) is a type of packet filtering that ensures network security by analyzing the packets flowing through the network and detecting any malicious pattern(s) present in them. In signature-based NIDS, pattern matching is the critical step as it determines the system’s performance. The throughput of the system, inherently, relies on the delay required to match an input pattern. Hardware-based high-speed pattern matching algorithms are popularly used to speed up the pattern matching process and improve the system’s performance. Ternary Content Addressable Memory (TCAM) is one such memory in which the input pattern is simultaneously launched on all the match lines. Since all the match lines and search lines are activated at a given instance, the power consumed per search is extremely high. To address this issue, this paper proposes an approach in which the match is carried out with an n-bit prefix of the input pattern that enables a smaller TCAM unit, which contains the patterns having this prefix. A significant improvement in energy is observed since a single TCAM segment is enabled for a single search. The results are compared with existing solutions, and energy improvement of 96.1% is observed with worst case and best case throughput of and , respectively.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.