Nested chopper instrument amplifier with noise modulation for physiological signal sensing

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-12-07 DOI:10.1016/j.vlsi.2024.102332

Bo Liu, Dong Zhang, Tianyu Liu, Kai Li, Jinchan Wang, Jun Wang

引用次数: 0

Abstract

This article presents a novel CMOS nested chopper instrumentation amplifier (NCIA) suitable for physiological signal (such as EEG, ECG and EMG) acquisition systems. By incorporating a DC offset suppression module and impedance boosting loop, the implemented instrumentation amplifier achieves high input impedance and low DC offset voltage. The usage of novel nested chopping technology with noise shifting in the filtering circuit effectively eliminates low-frequency noise, which makes it well-suited for analog front-end (AFE) sensing systems for precision extraction of weak physiological signals. The proposed NCIA circuit is implemented based on 180 nm/1.8 V standard BCD technology. Under 1.8V power supply voltage, the power consumption of the overall amplifier circuit is 4.17 μW, the total input reference noise is 771.365 nV_rms, and the total circuit layout area is 5.47 × 10⁻² mm².

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带噪声调制的嵌套斩波仪器放大器，用于生理信号传感

提出了一种适用于生理信号采集系统（如脑电图、心电和肌电）的新型CMOS嵌套斩波仪表放大器（NCIA）。通过集成直流失调抑制模块和阻抗提升回路，实现了高输入阻抗和低直流失调电压。采用新颖的嵌套斩波技术，在滤波电路中进行噪声移位，有效地消除了低频噪声，使其非常适合模拟前端（AFE）传感系统对微弱生理信号的精确提取。该NCIA电路基于180nm /1.8 V标准BCD技术实现。在1.8V供电电压下，整个放大电路的功耗为4.17 μW，总输入参考噪声为771.365 nVrms，电路总布局面积为5.47 × 10−2 mm2。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.