Design and implementation of a full analogue gate driver for current compensation of paralleled SiC-MOSFETs

IF 1.7 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Adel Rezaeian, Ahmad Afifi, Hamid Bahrami
{"title":"Design and implementation of a full analogue gate driver for current compensation of paralleled SiC-MOSFETs","authors":"Adel Rezaeian,&nbsp;Ahmad Afifi,&nbsp;Hamid Bahrami","doi":"10.1049/pel2.12834","DOIUrl":null,"url":null,"abstract":"<p>Silicon carbide MOSFETs have current ratings that are not sufficiently high to be used in high-power converters. It is necessary to connect several MOSFETs in parallel in order to increase current capabilities. However, transient imbalance peak currents during turn-on and -off processes challenge the performance and reliability of parallel MOSFETs. This paper considers the impact factors of device parameters, asymmetrical power circuit layout and circuit parasitic analytically to reveal the imbalance current peaks. The turn-on and -off transient conditions are studied and mathematically investigated. In master-slave configuration, a fully analogue active gate driver is designed and implemented to suppress the imbalance current among parallel silicon carbide (SiC) MOSFETs. In the proposed scheme, by exploiting an imbalance current detection circuit and I-controller in a negative feedback for the slave MOSFET, an appropriate control voltage is obtained. The output voltage of active gate driver is adjusted by the control voltage, whether positive or negative in turn-on and -off transient, in order to synchronize the peak currents of paralleled modules. Moreover, a detailed circuit of the designed compensator is presented and discussed. The experimental results are presented to verify the reliability and the effectiveness of the proposed compensator.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7000,"publicationDate":"2024-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.12834","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Power Electronics","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/pel2.12834","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

Silicon carbide MOSFETs have current ratings that are not sufficiently high to be used in high-power converters. It is necessary to connect several MOSFETs in parallel in order to increase current capabilities. However, transient imbalance peak currents during turn-on and -off processes challenge the performance and reliability of parallel MOSFETs. This paper considers the impact factors of device parameters, asymmetrical power circuit layout and circuit parasitic analytically to reveal the imbalance current peaks. The turn-on and -off transient conditions are studied and mathematically investigated. In master-slave configuration, a fully analogue active gate driver is designed and implemented to suppress the imbalance current among parallel silicon carbide (SiC) MOSFETs. In the proposed scheme, by exploiting an imbalance current detection circuit and I-controller in a negative feedback for the slave MOSFET, an appropriate control voltage is obtained. The output voltage of active gate driver is adjusted by the control voltage, whether positive or negative in turn-on and -off transient, in order to synchronize the peak currents of paralleled modules. Moreover, a detailed circuit of the designed compensator is presented and discussed. The experimental results are presented to verify the reliability and the effectiveness of the proposed compensator.

Abstract Image

用于并联sic - mosfet电流补偿的全模拟栅极驱动器的设计与实现
碳化硅mosfet的额定电流不够高,不能用于大功率变换器。为了增加电流能力,有必要并联几个mosfet。然而,在导通和关断过程中的瞬态不平衡峰值电流对并联mosfet的性能和可靠性提出了挑战。本文分析了器件参数、非对称功率电路布局和电路寄生等影响因素,揭示了不平衡电流峰值。对开关的暂态条件进行了研究和数学分析。在主从配置中,设计并实现了一个全模拟有源栅极驱动器,以抑制并联碳化硅mosfet之间的不平衡电流。在该方案中,利用不平衡电流检测电路和i -控制器对从MOSFET进行负反馈,获得合适的控制电压。有源栅极驱动器的输出电压由控制电压调节,无论是正电压还是负电压,在通断瞬态,以同步并联模块的峰值电流。此外,还给出了设计补偿器的详细电路。实验结果验证了该补偿器的可靠性和有效性。
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来源期刊
IET Power Electronics
IET Power Electronics ENGINEERING, ELECTRICAL & ELECTRONIC-
CiteScore
5.50
自引率
10.00%
发文量
195
审稿时长
5.1 months
期刊介绍: IET Power Electronics aims to attract original research papers, short communications, review articles and power electronics related educational studies. The scope covers applications and technologies in the field of power electronics with special focus on cost-effective, efficient, power dense, environmental friendly and robust solutions, which includes: Applications: Electric drives/generators, renewable energy, industrial and consumable applications (including lighting, welding, heating, sub-sea applications, drilling and others), medical and military apparatus, utility applications, transport and space application, energy harvesting, telecommunications, energy storage management systems, home appliances. Technologies: Circuits: all type of converter topologies for low and high power applications including but not limited to: inverter, rectifier, dc/dc converter, power supplies, UPS, ac/ac converter, resonant converter, high frequency converter, hybrid converter, multilevel converter, power factor correction circuits and other advanced topologies. Components and Materials: switching devices and their control, inductors, sensors, transformers, capacitors, resistors, thermal management, filters, fuses and protection elements and other novel low-cost efficient components/materials. Control: techniques for controlling, analysing, modelling and/or simulation of power electronics circuits and complete power electronics systems. Design/Manufacturing/Testing: new multi-domain modelling, assembling and packaging technologies, advanced testing techniques. Environmental Impact: Electromagnetic Interference (EMI) reduction techniques, Electromagnetic Compatibility (EMC), limiting acoustic noise and vibration, recycling techniques, use of non-rare material. Education: teaching methods, programme and course design, use of technology in power electronics teaching, virtual laboratory and e-learning and fields within the scope of interest. Special Issues. Current Call for papers: Harmonic Mitigation Techniques and Grid Robustness in Power Electronic-Based Power Systems - https://digital-library.theiet.org/files/IET_PEL_CFP_HMTGRPEPS.pdf
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