{"title":"A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving","authors":"Sihao Chen;Chengyu Huang;Limeng Sun;Yang Liu;Wenjun Tang;Jiaxuan Fan;Nan Sun;Yong Chen;Huazhong Yang;Xueqing Li","doi":"10.1109/TCSII.2024.3518084","DOIUrl":null,"url":null,"abstract":"This brief validates in silicon a four-channel non-return-to-zero (NRZ) output-overlapped (OO) time-interleaving (TI) digital-to-analog converter (DAC) for the first time. The proposed 4-ch TI DAC achieves a sampling rate (Fs) of 16-GS/s, with each sub-DAC operating at a speed of only Fs/4. Compared with conventional RZ structures, the proposed structure uses fewer clocks and avoids the use of high-speed clocks. Additionally, the output-overlapping design reduces DAC’s sensitivity to duty-cycle mismatches. The DAC was fabricated in 28nm CMOS, incorporating a low-complexity phase error correction (PEC) unit to ensure precise phase alignment for the sub-DACs. Experimental results demonstrate that this DAC achieves a spurious-free dynamic range (SFDR) of >60dBc (>40dBc) up to 2.3GHz (5.4GHz), representing a significant advancement over the state-of-the-art solutions within the 2.3GHz frequency range of interest.","PeriodicalId":13101,"journal":{"name":"IEEE Transactions on Circuits and Systems II: Express Briefs","volume":"72 2","pages":"374-378"},"PeriodicalIF":4.0000,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Circuits and Systems II: Express Briefs","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10802956/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This brief validates in silicon a four-channel non-return-to-zero (NRZ) output-overlapped (OO) time-interleaving (TI) digital-to-analog converter (DAC) for the first time. The proposed 4-ch TI DAC achieves a sampling rate (Fs) of 16-GS/s, with each sub-DAC operating at a speed of only Fs/4. Compared with conventional RZ structures, the proposed structure uses fewer clocks and avoids the use of high-speed clocks. Additionally, the output-overlapping design reduces DAC’s sensitivity to duty-cycle mismatches. The DAC was fabricated in 28nm CMOS, incorporating a low-complexity phase error correction (PEC) unit to ensure precise phase alignment for the sub-DACs. Experimental results demonstrate that this DAC achieves a spurious-free dynamic range (SFDR) of >60dBc (>40dBc) up to 2.3GHz (5.4GHz), representing a significant advancement over the state-of-the-art solutions within the 2.3GHz frequency range of interest.
期刊介绍:
TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:
Circuits: Analog, Digital and Mixed Signal Circuits and Systems
Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
Circuits and Systems, Power Electronics and Systems
Software for Analog-and-Logic Circuits and Systems
Control aspects of Circuits and Systems.