Memristor-Based Parallel Computing Circuit Optimization for LSTM Network Fault Diagnosis

Abstract

Researchers often focus on algorithmic enhancements while overlooking the potential benefits of hardware improvements. In this paper, a memristor-based parallel computing circuit optimization for LSTM network fault diagnosis is proposed. In response to the slow convergence of the algorithm, the characteristics of the memristor can matrix the algorithm and import it into the hardware circuit. The amnesia parallelization strategy executes four iterative processes simultaneously. The convergence speed is improved. Using the high-speed capability of the amnesia in parallel matrix operations using memristive circuits, four circuit modules are designed:mutation, crossover, evolution, and selection. These modules are integrated into a memristor circuit network model. To efficiently complete the iterative process and make effective use of the memristor’s strong storage property, the best-fit values are stored. To validate the effectiveness of the algorithm, simulations and comparative experiments are conducted on the Case Western Reserve University (CWRU) dataset. The results show that the model optimised with memristor hardware circuitry has improved the accuracy by 98% and has better fault diagnosis performance. This research not only advances the integration of memristive devices in neural network optimization, showcasing significant implications for the design of advanced circuit systems in the era of intelligent computing.