A calibration scheme for SAR ADCs based on capacitor weight optimization using an improved simulated annealing algorithm

Abstract

This paper proposes a foreground calibration method, which applies simulated annealing (SA) algorithm to the calibration of successive approximation register analog-to-digital converters (SAR ADCs). The capacitor weights are updated according to the performance metrics of the output codes, without necessitating any signal injection or modifying the analog structure of the SAR ADC. The methods of iterative and parallel solving, as well as variable searching step size are introduced into the SA calibration for adequate search. In addition, a multi-objective optimization strategy based on lexicographic optimization is used to take into account the performance of both signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The estimated capacitor weights are applied in the digital domain to calibrate the SAR ADC output codes. The effectiveness of this calibration method is verified by simulating a 12-bit SAR ADC model with 2-bit redundancy and calibrating a 16-bit, 500 kS/s SAR ADC with 4-bit redundancy fabricated in 180 nm technology. The simulation results show the significant improvements in both SNDR and SFDR, along with a notable enhancement in integral nonlinearity (INL). 512 sinusoidal signal samples are collected on testing platform to extract the capacitor weights that can further contribute to the calculation of the output codes. The experiment results show that the SNDR and SFDR are improved by 20.04 dB and 20.19 dB, respectively, while the INL are enhanced by nearly 16 LSB.