Design of lightweight on-chip one-dimensional convolutional neural network accelerators for edge-end chips

Abstract

One-dimensional convolutional neural networks (1D-CNNs) play a crucial role in edge computing applications. To address the challenges of deploying 1D-CNNs on edge devices, this paper proposes a lightweight on-chip 1D-CNN accelerator and its corresponding compilation and deployment process for edge-end chips. The proposed accelerator architecture features an innovative two-stage storage structure, a configurable multiplier-adder tree array, and a comparator array, with an integrated CORDIC core to enhance support for various 1D-CNN architectures. The compilation and deployment process supports operator conversion and fusion, increasing circuit utilization and reducing memory access demands. The accelerator was synthesized using the Global Foundries 22 nm process, achieving a peak throughput of 5.8 GOP/s and a power efficiency of 823.4 GOP/s/W at 200 MHz with an area of 0.056 mm². Comparative testing showed that the proposed design's average computation delay and energy efficiency are 0.520 and 0.145 times that of the ARM Cortex-M7, respectively, demonstrating the proposed accelerator's superior performance and energy efficiency.