Low-power 12T TFET-MOSFET hybrid SRAM bitcell and hybrid 8T SRAM array based on multiplexing strategy

Abstract

Due to the limitation of MOSFET subthreshold swing, traditional MOSFET-based static random-access memory (SRAM) circuits are difficult to meet the design requirements of low-power integrated circuits. To address these issues, we proposed a half-select disturb-free 12T TFET-MOSFET hybrid SRAM bitcell. It can avoid the forward p-i-n current and effectively mitigate the effect of current degradation, which greatly reduces the static power consumption of the circuit and improves the performance of SRAM. Specifically, compared to 12T, the write delay of the hybrid bitcell decreased by approximately 13.994 % at 0.6 V. Meanwhile, a TFET-MOSFET hybrid 8T SRAM array is proposed by a multiplexing strategy to reduce the area consumption. The proposed $4\times 4$ hybrid SRAM array is comparable to the 12T bitcell in terms of static noise margin (SNM), read/write speed, and static power consumption. These results indicate that the proposed TFET-MOSFET hybrid 8T SRAM array is a good choice for applications that require low power consumption and high stability.