An enhanced interlocked feedback structure-based dual-node upset resilient latch

Abstract

As the integrated circuit technology continues to scale down, the design of Double Node Upset (DNU) resilient latches has become a critical challenge in radiation-hardened design. Traditional designs of resilient latches are primarily based on the Dual Interlocked Storage Cell (DICE) and novel feedback mechanisms. However, these conventional approaches often suffer from significant limitations, such as instability or errors in logic states due to charge sharing during latching, or trade-offs among power consumption, delay, and area. To overcome these challenges, this paper proposes a DNU-resilient latch based on an enhanced interlocked feedback structure. The proposed ISR latch leverages its interlocked feedback mechanism to achieve self-recovery for the maximum number of double-node upset pairs. Simulation results based on the SMIC 28 nm process model demonstrate that the proposed latch can achieve self-recovery under any double-node disturbance. Compared to existing advanced DNU-resilient latches, the proposed design shows superior performance and power efficiency, achieving an average reduction of 81.67% in PDAP.