Implication logic synthesis and optimization methods for memristor-based logic circuits

Abstract

In this paper, we present an implication-driven logic synthesis framework to address the fanout problems and achieve a legal implication logic network optimized for minimal operational pulses and memristor count. We first incorporate a node-aware simulated annealing algorithm, utilizing an accurate cost function that considers fanout problem, to guide the technology mapping step in ABC. Additionally, after obtaining a strong initial implication logic network, we propose a method for the network optimization which primarily consists of two parts: exact synthesis to create an optimal database for all 4-input Boolean functions, and an improved heuristic algorithm to resolve any remaining fanout problem. We tested the optimization method over ISCAS’85 benchmarks, achieving an average reduction of 4% in operational pulses and 7% in memristors count compared to the state-of-the-art. Moreover, the experimental evaluations on a set of MCNC benchmarks show that our method reduces the operational pulses and memristors count on average by 21% and 22% over the state-of-the-art, respectively.