ITZO-Based Self-Aligned Top Gate Thin-Film Transistor with Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM.

Abstract

We developed a two-transistor, zero-capacitor (2T0C) gain-cell memory featuring a self-aligned top-gate-structured thin-film transistor (TFT) for the first time. The proposed indium tin zinc oxide (ITZO) channel-incorporated architecture was specifically engineered to minimize parasitic capacitance for achieving long-retention 2T0C memory operations. A typical 2T0C structure features five types of parasitic capacitances; however, the proposed SATG design effectively used an essential gate insulator capacitance (C _OX) and reduced four nonessential capacitances (C _WBL-WWL, C _WWL-SN, C _RWL-SN, and C _RBL-SN) to virtually zero. The ITZO-based 2T0C gain-cell memory achieved a retention time >10,000 s owing to the extremely low off-current (2.33 × 10^-18 A/μm), superior positive-bias stability (0.71 V), and high saturation mobility [17.52 cm²/(V s)] of the optimized TFT structure. Our proposed memory with long retention and high endurance is a promising solution for next-generation 3D-integrated stacked dynamic random-access memories and defines a new structural standard for future memory architectures.