A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-09-26 DOI:10.1109/TVLSI.2024.3458801

Chenjia Xie;Zhuang Shao;Ning Zhao;Xingyuan Hu;Yuan Du;Li Du

引用次数: 0

Abstract

Solving partial differential equations (PDEs) is omnipresent in scientific research and engineering and requires expensive numerical iteration for memory and computation. The primary concerns for solving PDEs are convergence speed, data movement, and power consumption. This work proposed the first fast-convergence PDE solver with an automatic adjustment multiple-stride iteration method, significantly increasing the PDE convergence speed. A dynamic-precision near-memory-computing architecture with booth encoding is proposed to reduce iterated intermediate data movement. A customized 32T compressor and a 14T full adder are designed to reduce the power and hardware cost of the solver. The processor is fabricated using 65-nm CMOS technology and occupies a 6.25 mm2 die area. It can achieve a convergence speedup by

$4\times $

compared with the existing work.

查看原文本刊更多论文

求解偏微分方程的快速收敛近内存计算加速器

求解偏微分方程在科学研究和工程中无处不在，需要昂贵的数值迭代来存储和计算。解决pde的主要关注点是收敛速度、数据移动和功耗。本文提出了首个采用自动调整多步迭代方法的快速收敛PDE求解器，显著提高了PDE的收敛速度。为了减少中间数据的重复移动，提出了一种采用booth编码的动态精度近内存计算体系结构。定制的32T压缩机和14T全加法器旨在降低求解器的功耗和硬件成本。该处理器采用65纳米CMOS技术制造，占地6.25 mm2的芯片面积。与现有的工作相比，它可以实现4倍的收敛速度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.