Shiro Dosho;Ludovico Minati;Kazuki Maari;Shungo Ohkubo;Hiroyuki Ito
{"title":"A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier","authors":"Shiro Dosho;Ludovico Minati;Kazuki Maari;Shungo Ohkubo;Hiroyuki Ito","doi":"10.1109/TVLSI.2024.3453314","DOIUrl":null,"url":null,"abstract":"The development of ultralow-power analog front ends for edge artificial intelligence (AI) is actively pursued; however, these front ends suffer from low-frequency selection accuracy, leading to increased training loads for the AI components and higher testing costs. In this article, we propose a novel circuit that fundamentally addresses these issues through direct conversion. By re-evaluating the circuit configurations of the multiplier, harmonic removal filter, and full-wave rectifier (FWR) from scratch, we have miniaturized and integrated an ultralow-power converter that transforms frequency components into pulse sequences. The frequency to be analyzed is determined by the local frequency input to the multiplier, which can be digitally controlled with high precision. In our system, the Q value is adaptively adjusted by the local frequency of the direct conversion, allowing the same circuit configuration to be applied to all frequency nodes, eliminating the need for filter design for each node and providing a highly design-friendly and scalable frequency analysis system.The test chip was fabricated with a 0.18-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m process, operating at a 1.2-V supply, and outputting power pulse streams corresponding to 11 different frequencies ranging from 500 to 5 kHz. The total operating power was <inline-formula> <tex-math>$0.9\\mu $ </tex-math></inline-formula>W, with an achieved equivalent Q factor ranging from 3.6 to 36. In a training experiment using a convolutional neural network (CNN) speech recognition model constructed with a functional model equivalent to this front end, a recognition rate exceeding 80% was achieved, demonstrating the practicality of this front end.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 2","pages":"315-325"},"PeriodicalIF":2.8000,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10695034","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10695034/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The development of ultralow-power analog front ends for edge artificial intelligence (AI) is actively pursued; however, these front ends suffer from low-frequency selection accuracy, leading to increased training loads for the AI components and higher testing costs. In this article, we propose a novel circuit that fundamentally addresses these issues through direct conversion. By re-evaluating the circuit configurations of the multiplier, harmonic removal filter, and full-wave rectifier (FWR) from scratch, we have miniaturized and integrated an ultralow-power converter that transforms frequency components into pulse sequences. The frequency to be analyzed is determined by the local frequency input to the multiplier, which can be digitally controlled with high precision. In our system, the Q value is adaptively adjusted by the local frequency of the direct conversion, allowing the same circuit configuration to be applied to all frequency nodes, eliminating the need for filter design for each node and providing a highly design-friendly and scalable frequency analysis system.The test chip was fabricated with a 0.18-$\mu $ m process, operating at a 1.2-V supply, and outputting power pulse streams corresponding to 11 different frequencies ranging from 500 to 5 kHz. The total operating power was $0.9\mu $ W, with an achieved equivalent Q factor ranging from 3.6 to 36. In a training experiment using a convolutional neural network (CNN) speech recognition model constructed with a functional model equivalent to this front end, a recognition rate exceeding 80% was achieved, demonstrating the practicality of this front end.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.