A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-09 DOI:10.1109/TVLSI.2024.3465010

Zihang Wang;Yushu Yang;Jianfei Wang;Jia Hou;Yang Su;Chen Yang

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引用次数: 0

Abstract

Polynomial multiplication is a significant bottleneck in mainstream postquantum cryptography (PQC) schemes. To speed it up, number theoretic transform (NTT) is widely used, which decreases the time complexity from

${O}(n^{2})$

$O[n\log _{2}(n)]$

. However, it is challenging to ensure optimal hardware efficiency in conjunction with scalability. This brief proposes a novel pipelined NTT/inverse-NTT (INTT) architecture on field-programmable gate array (FPGA). A group-based pairwise memory access (GPMA) scheme is proposed, and a scratchpad and reordering unit (SRU) is designed to form an efficient dataflow that simplifies control units and achieves almost

$n/2$

processing cycles on average for n-point NTT. Moreover, our architecture can support varying parameters. Compared to the state-of-the-art works, our architecture achieves up to

$4.8\times $

latency improvements and up to

$4.3\times $

improvements on area time product (ATP).

查看原文本刊更多论文

基于组对存储器访问和快速级间重排序的可扩展高效NTT/INTT体系结构

多项式乘法是后量子加密（PQC）的主要瓶颈。为了提高速度，广泛采用数论变换（number theoretical transform， NTT），将时间复杂度从${O}(n^{2})$降低到$O[n\log _{2}(n)]$。然而，要确保结合可伸缩性的最佳硬件效率是一项挑战。本文提出了一种基于现场可编程门阵列（FPGA）的新型流水线NTT/反NTT （INTT）架构。提出了一种基于组的两两存储器访问（GPMA）方案，并设计了一个刮记板和重新排序单元（SRU），以形成一个高效的数据流，简化了控制单元，并在n点NTT中平均实现了近$n/2$的处理周期。此外，我们的体系结构可以支持各种参数。与最先进的作品相比，我们的架构实现了高达4.8倍的延迟改进和高达4.3倍的面积时间积（ATP）改进。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.