A Half-Schmitt Trigger-Based 9T1R Nonvolatile Robust SRAM Cell for Instant On-Off Application

Abstract

This article proposes a novel design of 9T1R nonvolatile static random access memory (nvSRAM). The proposed nvSRAM cell significantly improves critical performance metrics such as static noise margin, read-delay, break-even time (BET), and store/restore delay/energy. Schmitt trigger action is enabled during read to mitigate read disturb problem and improve read static noise margin. A resistive random access memory (RRAM) device is used intelligently to store/restore data in a single cycle. The technique reduces the store and restore delay by 50% and 25% compared to its nearest competitor nvSRAM. The Monte-Carlo simulations demonstrate a very reliable read/write operation with lower variability ( $\sigma /\mu $ ) and improved effective mean ( $\mu - 3\sigma $ ) compared to existing nvSRAMs. The Worst-case corner analysis under extreme temperatures confirms the robustness of the design in face of PVT variations. The proposed design incurs only 40% area overhead as compared to 6T cell, which is much smaller than several other existing nvSRAMs. A new figure of merit that comprehensively captures cell-stability, write-ability, read/write/store/restore delay & power dissipation of an nvSRAM cell is also proposed. Based on this metric, it is observed that the proposed cell outperforms all of the nvSRAM cells considered in this work. Array simulations for a 1Mb nvSRAM at both typical and slow process corners demonstrate minimal store/restore delay overheads and favorable access times, supporting its suitability for applications requiring instant on-off functionality.