A D-Band Differential Phase Shifter Based on a Transmission Delay Line With Variable Inductors and Capacitors

0 ENGINEERING, ELECTRICAL & ELECTRONIC
Ilgwon Kim;Hyunji Koo;Wansik Kim;Songcheol Hong
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引用次数: 0

Abstract

A transmission delay line (TDL) differential phase shifter (PS) with 5-bit resolution, operating at D-band frequencies (120–146 GHz), is proposed. It provides bi-directional 180° phase shift characteristics with $50~\Omega $ input/output impedances. It consists of eight LC cells. Each unit cell has a series inductor and two shunt capacitors. The inductance is controlled with a switched coupled inductor (SCI), and the capacitances are controlled with variable capacitors. The 1st to 6th cells are identical, where a unit cell provides a 22.5° phase shift. The 7th and 8th cells are for phase shifts of 11.25°/22.5° and 5.625°/11.25°, respectively. These are achieved by using dual-switched coupled inductors (DSCI) and varactors in each cell. The proposed PS is designed in a 40-nm CMOS process, occupying 0.24 mm2 including I/O pads with a core size of 0.09 mm2. The maximum measured insertion loss was −17.2 dB at 142 GHz, and the loss variation across all 33 phases was within 1.5 dB.
基于可变电感和电容传输延迟线的d波段差分移相器
提出了一种5位分辨率的传输延迟线差分移相器(PS),工作在d频段(120-146 GHz)。它提供双向180°相移特性,输入/输出阻抗为$50~\Omega $。它由8个LC单元组成。每个单元电池有一个串联电感器和两个并联电容器。电感由开关耦合电感(SCI)控制,电容由可变电容控制。第1到第6个电池是相同的,其中一个单元电池提供22.5°相移。第7和第8单元的相移分别为11.25°/22.5°和5.625°/11.25°。这是通过在每个电池中使用双开关耦合电感(DSCI)和变容管来实现的。所提出的PS采用40纳米CMOS工艺设计,占地0.24 mm2,包括内核尺寸为0.09 mm2的I/O焊盘。在142 GHz时,测量到的最大插入损耗为- 17.2 dB,所有33个相位的损耗变化在1.5 dB以内。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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CiteScore
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