An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-01 DOI:10.1109/TVLSI.2024.3464870

Jinghai Wang;Shanlin Xiao;Jilong Luo;Bo Li;Lingfeng Zhou;Zhiyi Yu

{"title":"An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS","authors":"Jinghai Wang;Shanlin Xiao;Jilong Luo;Bo Li;Lingfeng Zhou;Zhiyi Yu","doi":"10.1109/TVLSI.2024.3464870","DOIUrl":null,"url":null,"abstract":"Asynchronous circuits with low power and robustness are revived in emerging applications such as the Internet of Things (IoT) and neuromorphic chips, thanks to clock-less and event-driven mechanisms. However, the lack of mature computer-aided design (CAD) tools for designing large-scale asynchronous circuits results in low design efficiency and high cost. This article proposes an end-to-end bundled-data (BD) asynchronous circuit design flow, which can facilitate building asynchronous circuits, even if the designer has little or no asynchronous circuit foundation. Three features that enable this are: 1) a lightweight circuit converter developed in Python can convert circuits from synchronous descriptions to corresponding asynchronous ones at register transfer level (RTL). Desynchronization flow helps designers maintain a “synchronization mentality” to construct asynchronous circuits; 2) a synchronization-like verification method is proposed for asynchronous circuits so that it can be functionally verified before synthesis. Avoids the risk of rework after logic defects are discovered during the synthesis and implementation, as asynchronous circuits often cannot be simulated until gate-level (GL) netlist generation; and 3) the whole implementation flow from RTL to graphic data system (GDS) is based on commercial electronic design automation (EDA) tools. Similar to the design flow of synchronous circuits, it helps designers implement asynchronous circuits with “synchronization habits.” Furthermore, to validate this methodology, two asynchronous processors were, respectively, implemented and evaluated in the TSMC 28-nm CMOS process. Compared to their synchronous counterparts, the general-purpose asynchronous RISC-V processor achieves 20.5% power savings. And the domain-specific asynchronous spiking neural network (SNN) accelerator achieves 58.46% power savings and \n<inline-formula> <tex-math>$2.41\\times $ </tex-math></inline-formula>\n energy efficiency improvement at 70% input spike sparsity.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"154-167"},"PeriodicalIF":2.8000,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10701060/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

Asynchronous circuits with low power and robustness are revived in emerging applications such as the Internet of Things (IoT) and neuromorphic chips, thanks to clock-less and event-driven mechanisms. However, the lack of mature computer-aided design (CAD) tools for designing large-scale asynchronous circuits results in low design efficiency and high cost. This article proposes an end-to-end bundled-data (BD) asynchronous circuit design flow, which can facilitate building asynchronous circuits, even if the designer has little or no asynchronous circuit foundation. Three features that enable this are: 1) a lightweight circuit converter developed in Python can convert circuits from synchronous descriptions to corresponding asynchronous ones at register transfer level (RTL). Desynchronization flow helps designers maintain a “synchronization mentality” to construct asynchronous circuits; 2) a synchronization-like verification method is proposed for asynchronous circuits so that it can be functionally verified before synthesis. Avoids the risk of rework after logic defects are discovered during the synthesis and implementation, as asynchronous circuits often cannot be simulated until gate-level (GL) netlist generation; and 3) the whole implementation flow from RTL to graphic data system (GDS) is based on commercial electronic design automation (EDA) tools. Similar to the design flow of synchronous circuits, it helps designers implement asynchronous circuits with “synchronization habits.” Furthermore, to validate this methodology, two asynchronous processors were, respectively, implemented and evaluated in the TSMC 28-nm CMOS process. Compared to their synchronous counterparts, the general-purpose asynchronous RISC-V processor achieves 20.5% power savings. And the domain-specific asynchronous spiking neural network (SNN) accelerator achieves 58.46% power savings and

$2.41\times $

energy efficiency improvement at 70% input spike sparsity.

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端到端捆绑数据异步电路设计流程：从RTL到GDS

由于采用了无时钟和事件驱动机制，具有低功耗和鲁棒性的异步电路在物联网（IoT）和神经形态芯片等新兴应用中焕发出新的活力。然而，由于缺乏成熟的计算机辅助设计（CAD）工具来设计大规模异步电路，导致设计效率低、成本高。本文提出了一种端到端捆绑数据（BD）异步电路设计流程，即使设计者几乎没有异步电路基础，也能轻松构建异步电路。实现这一点的三个特点是1) 在 Python 中开发的轻量级电路转换器可在寄存器传输层（RTL）将电路从同步描述转换为相应的异步描述。去同步化流程可帮助设计人员保持 "同步心态 "来构建异步电路；2）针对异步电路提出了一种类似同步的验证方法，以便在综合之前对其进行功能验证。避免了在综合和实现过程中发现逻辑缺陷后返工的风险，因为异步电路通常要到门级（GL）网表生成后才能进行仿真；以及 3) 从 RTL 到图形数据系统（GDS）的整个实现流程都基于商用电子设计自动化（EDA）工具。与同步电路的设计流程类似，它可以帮助设计人员实现具有 "同步习惯 "的异步电路。此外，为了验证这种方法，分别在台积电 28 纳米 CMOS 工艺中实现并评估了两个异步处理器。与同步处理器相比，通用异步 RISC-V 处理器的功耗降低了 20.5%。而特定领域的异步尖峰神经网络（SNN）加速器在 70% 输入尖峰稀疏度的条件下实现了 58.46% 的功耗节省和 2.41 美元/次的能效提升。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.