A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-11 DOI:10.1109/TVLSI.2024.3508673

Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta

{"title":"A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation","authors":"Zhichao Chen;Ali H. Hassan;Rhesa Ramadhan;Yingheng Li;Chih-Kong Ken Yang;Sudhakar Pamarti;Puneet Gupta","doi":"10.1109/TVLSI.2024.3508673","DOIUrl":null,"url":null,"abstract":"Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by \n<inline-formula> <tex-math>$15\\times $ </tex-math></inline-formula>\n to over \n<inline-formula> <tex-math>$23.8\\times $ </tex-math></inline-formula>\n depending on performance level. Alternatively, LT improves performance by \n<inline-formula> <tex-math>$2.4\\times $ </tex-math></inline-formula>\n (high-power, high-performance) \n<inline-formula> <tex-math>$- 7.0\\times $ </tex-math></inline-formula>\n (low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in \n<inline-formula> <tex-math>$V_{\\text {th}}$ </tex-math></inline-formula>\n variation to leverage benefits at cryogenic temperatures.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 1","pages":"102-113"},"PeriodicalIF":2.8000,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10787912/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

Low-temperature (LT) conditions can potentially lead to lower power consumption and enhanced performance in circuit operations by reducing the transistor leakage current, increasing carrier mobility, reducing wear-out, and reducing interconnect resistance. We develop PROCEED-LT, a pathfinding framework to co-optimize devices and circuits over a wide performance range. Our results demonstrate that circuit operations at LT (−196 °C) reduce power compared to room temperature (RT, 85 °C) by

$15\times $

to over

$23.8\times $

depending on performance level. Alternatively, LT improves performance by

$2.4\times $

(high-power, high-performance)

$- 7.0\times $

(low-power, low-performance) at the same power point. These gains are further improved in low-activity circuits and when using multivoltage configurations. Meanwhile, we highlight the need for improvement in

$V_{\text {th}}$

variation to leverage benefits at cryogenic temperatures.

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低温与室温电路运行的比较分析

低温（LT）条件可以通过减少晶体管泄漏电流、增加载流子迁移率、减少损耗和降低互连电阻，从而潜在地降低功耗并增强电路操作的性能。我们开发了PROCEED-LT，这是一种寻路框架，用于在广泛的性能范围内共同优化器件和电路。我们的研究结果表明，与室温（RT, 85°C）相比，在LT（- 196°C）下的电路操作可将功耗降低15美元至23.8美元以上，具体取决于性能水平。另外，在相同的功率点上，LT将性能提高了2.4倍（高功率，高性能）- 7.0倍（低功率，低性能）。这些增益在低活度电路和使用多电压配置时得到进一步改善。同时，我们强调需要改进$V_{\text {th}}$变化以利用低温下的优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.