A 6–64-Gb/s 0.41-pJ/Bit Reference-Less PAM4 CDR Using a Frequency-Detection-Gain-Enhanced PFD Achieving 19.8-Gb/s/μs Acquisition Speed

Abstract

This brief presents a wideband continuous-rate reference-less ring-oscillator-based PAM4 CDR. Our proposed frequency-detection-gain-enhanced phase/frequency detector (GE-PFD), in which only two logic gates are added to the Alexander bang-bang phase detector, significantly speeds up the frequency acquisition process of our CDR with wide capture range by controlling an auxiliary charge pump (A-CP). This technique eliminates separate FD or extra clock phases in prior PFDs, thus saving power. Fabricated in a 40-nm CMOS process, our CDR prototype achieves 6-64-Gb/s data rate range, 19.8-Gb/s/ $\mu $ s acquisition speed, and <10–12 bit error rate with a PRBS-31 input stream. The energy efficiency is 0.41-pJ/bit, in which only 0.02 pJ/bit is contributed by the extra logic gates of the FDGE-PFD and A-CP.