Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC
Kaisarbek Omirzakhov;Han Hao;Ali Pirmoradi;Firooz Aflatouni
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引用次数: 0

Abstract

This work presents a monolithically integrated eight-channel optical transmitter in the optical C-band. It supports up to 256 Gb/s aggregate data rate using two-section p-n-capacitive micro-ring modulators (MRMs) integrated together with wavelength stabilization circuit, data generator, and high swing electrical drivers on the same CMOS silicon-on-insulator (SOI) chip. The MRMs have an extinction ratio of >10 dB and a quality factor of about 5000 and can be capacitively tuned over about 400 pm with near-zero power consumption. The energy efficiency of the modulator, including per-channel capacitive wavelength tuning and locking, is 15 fJ/bit at 5-Gb/s/channel and 63 fJ/bit at 32-Gb/s/channel for a bit error rate (BER) ${\lt } 10{^{-12}}$ and the energy efficiency of the transmitter is 328 fJ/b at 32 Gb/s and 113 fJ/b at 10 Gb/s for a BER ${\lt }~10{^{-12}}$ . The areal bandwidth density of the modulator unit (including MRMs and the driver electronics) and the core area (including MRMs, drivers, electrical and optical routing, control, and data management electronics) are about 13.25 and 3.3 Tb/s/mm2, respectively. The chip is implemented on a 45 nm CMOS SOI process within a footprint of $1.2 {\times } 0.5$ mm.
具有自主波长稳定的45nm CMOS SOI节能单片集成256gb /s光发射机
本文提出了一种光c波段单片集成的八通道光发射机。它支持高达256gb /s的总数据速率,采用两段p-n电容微环调制器(MRMs),将波长稳定电路、数据发生器和高摆幅电驱动器集成在同一个CMOS绝缘体上硅(SOI)芯片上。mrm的消光比为10db,质量因数约为5000,可以在400 pm左右进行电容调谐,功耗接近于零。当误码率(BER) ${\lt} 10{^{-12}}$时,调制器的能量效率为32gb /s时328 fJ/b,当误码率${\lt}~10{^{-12}}$时,发射器的能量效率为10gb /s时113 fJ/b。调制器单元(包括mrm和驱动电子元件)和核心区(包括mrm、驱动器、电气和光路由、控制和数据管理电子元件)的面带宽密度分别约为13.25和3.3 Tb/s/mm2。该芯片采用45纳米CMOS SOI工艺,占地面积为1.2 × 0.5 mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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