Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-10-21 DOI:10.1109/TVLSI.2024.3475810

Jere Rusanen;Negar Shabanzadeh;Aarno Pärssinen;Timo Rahkonen;Janne P. Aikio

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引用次数: 0

Abstract

This article presents an integrated quadrature balanced power amplifier (PA) operating at a 26-GHz frequency range and techniques to mitigate the frequency-dependent amplitude response of quadrature hybrids used in the balanced amplifier design. The overall structure consists of two stacked pseudo-differential PAs and transformer-based quadrature hybrids designed with 22-nm CMOS FDSOI. Two techniques to compensate frequency-dependent amplitude response of the quadrature hybrid when operating away from the center frequency are proposed. The first one involves a dual input drive and the second one involves asymmetric biasing. With distortion contribution analysis, it is shown that asymmetric biasing compensates quadrature hybrid asymmetry but also produces mutually compensating third-order nonlinearity, resulting in improved linearity. Measurements with continuous wave (CW) and high dynamic range fifth generation (5G) modulated signal demonstrate that the described techniques improve output power that can be reached within the linearity specifications when operating away from the center frequency.

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通过补偿正交杂化失配效应改善ka波段集成平衡功率放大器性能

本文介绍了一种在 26 GHz 频率范围内工作的集成正交平衡功率放大器 (PA)，以及减轻平衡放大器设计中使用的正交混合放大器的频率相关振幅响应的技术。整体结构包括两个堆叠式伪差分功率放大器和基于变压器的正交混合放大器，采用 22 纳米 CMOS FDSOI 设计。在远离中心频率工作时，提出了两种补偿正交混合放大器频率相关振幅响应的技术。第一种涉及双输入驱动，第二种涉及非对称偏置。通过失真贡献分析表明，非对称偏置不仅能补偿正交混合放大器的不对称，还能产生相互补偿的三阶非线性，从而提高线性度。连续波（CW）和高动态范围第五代（5G）调制信号的测量结果表明，所述技术提高了输出功率，在远离中心频率工作时，输出功率可达到线性度规范要求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.