Two nanometre CMOS technology

IF 33.7 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

Nature Electronics Pub Date : 2024-12-09 DOI:10.1038/s41928-024-01320-y

Owain Vaughan

引用次数: 0

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二纳米CMOS技术

对于台积电，Geoffrey Yeap及其同事报告了一个2nm逻辑平台。基于栅极全能纳米片晶体管，它具有可扩展的铜基再分布层和平坦钝化层，以及硅通孔。与他们之前在2022年IEEE国际电子器件会议上报告的3nm技术节点相比，该平台的芯片密度增加了约1.15倍，速度提高了约15%，功耗降低了约30%。计划于2025年下半年量产。对于英特尔，Ashish Agrawal和他的同事报告了栅极全能带状晶体管（英特尔版本的纳米片晶体管），栅极长度为6纳米，接触多间距（相邻晶体管栅极之间的间距）为45纳米。他们表明，器件中的电子迁移率不会降低到3纳米的硅厚度，在3纳米以下，由于表面粗糙度导致的电子散射成为一个问题。

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来源期刊

Nature Electronics Engineering-Electrical and Electronic Engineering

CiteScore

47.50

自引率

2.30%

发文量

159

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