A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das
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引用次数: 0

Abstract

Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by $2.1\times $ , latency by $40\times $ , and interconnect area by $2\times $ , compared to a state-of-the-art interconnect for neuromorphic systems.
面向神经形态体系结构的可扩展动态分段总线互连
大规模的神经形态架构由计算块组成,这些计算块使用共享互连来传递峰值。我们提出了一种动态分段总线互连,以解决设计的可扩展性,同时降低峰值流量的能量和延迟。ADIONA由平行的公交车道组成,排列成阶梯状结构,允许任何瓷砖连接到另一个瓷砖,为通信链路提供多种路由选择,并为不同的映射场景和用例提供高水平的定制。梯式总线中的每个通道都使用轻量级无缓冲交换机划分成段。基于编译时通信信息,可以在运行时动态地重新配置这些开关,以执行目标应用程序。我们的动态分段总线互连大大提高了硬件利用率,提高了容错性,并提供了在单个硬件平台上执行不同应用程序的适应性。我们在一个周期精确的神经形态模拟器上使用三个合成和三个现实的机器学习工作负载来评估ADIONA。我们的研究结果表明,与最先进的神经形态系统互连相比,ADIONA可将能耗降低2.1倍,延迟降低40倍,互连面积降低2倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
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