A High-Efficiency Crosstalk Control Method of the Staggered High-Speed via Array in PCB for Chiplet-Based System

IF 2 3区计算机科学 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electromagnetic Compatibility Pub Date : 2024-12-04 DOI:10.1109/TEMC.2024.3502412

Ruan Jiang;Xianglong Wang;DongDong Chen;DI Li;Yingtang Yang

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Abstract

In this research, a high-efficiency crosstalk control method of the staggered high-speed via array in printed circuit board for Chiplet-based system is developed based on the neural network (NN) model and particle swarm optimization (PSO) algorithm. Based on the high frequency structure simulator (HFSS) and Q3D software, the simulation results of the staggered high-speed via array are obtained. The complex relationship among the structural parameters, crosstalk indexes, and characteristic impedance of the staggered high-speed via array is described by NN model. Then, the structural parameters of the staggered high-speed via array are optimized by PSO algorithm according to the multiobjective function including eight crosstalk indexes and eight characteristic impedance indexes. According to the optimized structural parameters, the effectiveness is verified through the finite element simulation. The simulated indexes agree with the desired indexes. In the four cases, the maximum error between the simulated and optimized indexes is 2.00%, which indicates that the developed method can accurately optimize the structural parameters of the staggered high-speed via array to control the crosstalk and characteristic impedance. Therefore, the developed high-efficiency design method can achieve the performance indexes control of the staggered high-speed via array, which can improve the performance of Chiplet-based system.

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基于芯片系统的PCB交错高速通孔阵列的高效串扰控制方法

基于神经网络（NN）模型和粒子群优化（PSO）算法，提出了一种适用于芯片系统的印刷电路板交错高速通孔阵列的高效串扰控制方法。基于高频结构模拟器（HFSS）和Q3D软件，得到了交错高速通孔阵列的仿真结果。利用神经网络模型描述了交错高速通孔阵列的结构参数、串扰指标和特性阻抗之间的复杂关系。然后，根据包含8个串扰指标和8个特征阻抗指标的多目标函数，利用粒子群算法对交错高速通孔阵列的结构参数进行优化。根据优化后的结构参数，通过有限元仿真验证了优化的有效性。模拟的索引与期望的索引一致。在四种情况下，仿真指标与优化指标之间的最大误差为2.00%，表明所开发的方法可以准确地优化交错高速通孔阵列的结构参数，以控制串扰和特性阻抗。因此，所开发的高效设计方法可以实现交错高速通孔阵列的性能指标控制，从而提高基于单片机的系统的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Electromagnetic Compatibility 工程技术-电信学

CiteScore

4.80

自引率

19.00%

发文量

235

审稿时长

2.3 months

期刊介绍： IEEE Transactions on Electromagnetic Compatibility publishes original and significant contributions related to all disciplines of electromagnetic compatibility (EMC) and relevant methods to predict, assess and prevent electromagnetic interference (EMI) and increase device/product immunity. The scope of the publication includes, but is not limited to Electromagnetic Environments; Interference Control; EMC and EMI Modeling; High Power Electromagnetics; EMC Standards, Methods of EMC Measurements; Computational Electromagnetics and Signal and Power Integrity, as applied or directly related to Electromagnetic Compatibility problems; Transmission Lines; Electrostatic Discharge and Lightning Effects; EMC in Wireless and Optical Technologies; EMC in Printed Circuit Board and System Design.