A novel structure of less switching loss IGBT with super junction

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-11-10 DOI:10.1016/j.mejo.2024.106477

Bokang Huang, Quanyuan Feng, Qiqi Liu, Zhiyong Qiu

{"title":"A novel structure of less switching loss IGBT with super junction","authors":"Bokang Huang, Quanyuan Feng, Qiqi Liu, Zhiyong Qiu","doi":"10.1016/j.mejo.2024.106477","DOIUrl":null,"url":null,"abstract":"<div><div>In order to further reduce the switching loss (E<sub>SW</sub>), a novel floating CS layer and super-junction insulated gate bipolar transistor (FCS-SJBJ-IGBT) with internal barrier junction is proposed and simulated. On the premise of not affecting breakdown voltage (BV), the CS layer of FCS-SJBJ-IGBT is floating, so that the P-body is connected with the P-drift region, and a small part of P-pillar is formed between the CS layer and the left gate, which enables electrons to flow rapidly through this region in the on state, and provides an extraction hole path in the off state to reduce the loss. The simulation results show that，under the same forward conduction voltage (V<sub>ON</sub>) condition, the turn-on energy loss (E<sub>ON</sub>) of FCS-SJBJ-IGBT is significantly lower than that of the traditional super-junction IGBT (con-SJ-IGBT) and 34.5 % lower than that of the recently reported super-junction IGBT (SJBJ-IGBT) with blocking junction, P-pillar and N-pillar, while their turn-off energy loss (E<sub>OFF</sub>) is almost the same. The research results can provide important reference for reducing the E<sub>SW</sub> of IGBT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106477"},"PeriodicalIF":1.9000,"publicationDate":"2024-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124001814","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

In order to further reduce the switching loss (E_SW), a novel floating CS layer and super-junction insulated gate bipolar transistor (FCS-SJBJ-IGBT) with internal barrier junction is proposed and simulated. On the premise of not affecting breakdown voltage (BV), the CS layer of FCS-SJBJ-IGBT is floating, so that the P-body is connected with the P-drift region, and a small part of P-pillar is formed between the CS layer and the left gate, which enables electrons to flow rapidly through this region in the on state, and provides an extraction hole path in the off state to reduce the loss. The simulation results show that，under the same forward conduction voltage (V_ON) condition, the turn-on energy loss (E_ON) of FCS-SJBJ-IGBT is significantly lower than that of the traditional super-junction IGBT (con-SJ-IGBT) and 34.5 % lower than that of the recently reported super-junction IGBT (SJBJ-IGBT) with blocking junction, P-pillar and N-pillar, while their turn-off energy loss (E_OFF) is almost the same. The research results can provide important reference for reducing the E_SW of IGBT.

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一种具有超级结的低开关损耗IGBT新结构

为了进一步降低开关损耗（ESW），提出并仿真了一种具有内势垒结的新型悬浮CS层超结绝缘栅双极晶体管（FCS-SJBJ-IGBT）。在不影响击穿电压（BV）的前提下，FCS-SJBJ-IGBT的CS层是浮动的，使p体与p漂移区相连，CS层与左栅极之间形成一小部分p柱，使电子在导通状态下快速流过该区域，在关断状态下提供抽吸空穴路径，降低损耗。仿真结果表明，在相同正向传导电压（VON）条件下，FCS-SJBJ-IGBT的导通能量损失（EON）明显低于传统的超结IGBT (con-SJ-IGBT)，比最近报道的具有阻塞结、p柱和n柱的超结IGBT （SJBJ-IGBT）低34.5%，而它们的关断能量损失（EOFF）几乎相同。研究结果可为减小IGBT的ESW提供重要参考。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.