UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor

Abstract

Most SNN hardware implementations adopt a heterogeneous architecture consisting of CPUs and accelerators to achieve efficiency in neuromorphic computing. However, this architectural method encounters challenges like load imbalance, communication delays, and substantial demand for hardware resources. To address this issue, we build a unified model description framework and processing architecture, the unified integration core (UIC), which integrates neuromorphic computing (NC) and general-purpose computing (GPC), and conduct software and hardware co-design. By implementing a set of integration and transformation operations, UIC can support critical general purpose processor (GPP) and SNN operations with the same processing elements achieving significant area reduction and latency reduction over those of a naive implementation. A compatible communication infrastructure is proposed to enable homogeneous and heterogeneous scalability on a decentralized intra- and inter-core network. Several optimization methods are incorporated, including resource and data sharing, near-memory processing, and intra-/inter-core pipeline. Compared to the previous state-of-the-art works, UIC achieves high energy efficiency at 2.55 mJ/inference with a low latency of 18.4 ms. In terms of hardware resource consumption, LUTs, and FF hardware resources are reduced by 56% and 60%.