Line-tunneling based GaP/Si heterostructure vertical gate-all-around tunnel FET for enhanced electrical performance

Abstract

This study explores strategies to enhance Tunnel FET performance through innovative device geometry and heterostructure integration. The use of a GaP/Si heterostructure, combined with a heavily doped n + source pocket, significantly boosts BTBT (band-to-band tunneling). The gate, which completely surrounds the source, induces line-tunneling and improves gate control over the tunnel junction, further contributing to enhanced device performance. The incorporation of a gate-drain underlap architecture and a vertically oriented design effectively suppresses ambipolar and leakage currents, resulting in an increased current ratio, reduced subthreshold slope (SS), and a minimized device footprint. Comparative analysis with existing TFET architectures shows that the optimized device achieves promising results, including an average SS of 13 mV/decade, an off-current (I_off) of 2.36 $\times$ 10^-17 A, an on-current (I_on) of 2.1 $\times$ 10^-5 A, and an ambipolar current (I_amb) of 3.28 $\times$ 10^-16 A.