SPGPU: Spatially Programmed GPU

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2024-11-14 DOI:10.1109/LCA.2024.3499339

Shizhuo Zhu;Illia Shkirko;Jacob Levinson;Zhengrong Wang;Tony Nowatzki

引用次数: 0

Abstract

Communication is a critical bottleneck for GPUs, manifesting as energy and performance overheads due to network-on-chip (NoC) delay and congestion. While many algorithms exhibit locality among thread blocks and accessed data, modern GPUs lack the interface to exploit this locality: GPU thread blocks are mapped to cores obliviously. In this work, we explore a simple extension to the conventional GPU programming interface to enable control over the spatial placement of data and threads, yielding new opportunities for aggressive locality optimizations within a GPU kernel. Across 7 workloads that can take advantage of these optimizations, for a 32 (or 128) SM GPU: we achieve a 1.28× (1.54×) speedup and 35% (44%) reduction in NoC traffic, compared to baseline non-spatial GPUs.

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SPGPU：空间编程 GPU

通信是 GPU 的一个关键瓶颈，由于片上网络（NoC）延迟和拥塞，通信表现为能耗和性能开销。虽然许多算法在线程块和访问数据之间表现出局部性，但现代 GPU 缺乏利用这种局部性的接口：GPU 线程块是被无意识地映射到内核上的。在这项工作中，我们探索了对传统 GPU 编程接口的简单扩展，以实现对数据和线程空间位置的控制，为在 GPU 内核中进行积极的位置优化提供新的机会。与基线非空间 GPU 相比，在 7 种可利用这些优化的工作负载中，对于 32（或 128）SM GPU，我们实现了 1.28 倍（1.54 倍）的速度提升和 35%（44%）的 NoC 流量减少。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.