A high interference-rejection receiver front-end for 5G applications using novel architecture and compact zero-pole filtering circuit topology

Abstract

This paper presents a high interference-rejection receiver front-end in 0.15-$\mu$m GaAs pHEMT process for 5G applications. We propose a novel architecture to improve the selectivity of the receiver front-end, thereby enhancing its interference-rejection capability. The design strategy of this novel architecture is to split the functions of the high-selectivity filter and distribute them into the individual devices within the receiver front-end, and then employ the more compact zero-pole filtering circuit topology to implement and merge these split functions. This enables us to achieve the equivalent integration of the high-selectivity filter within the receiver front-end while maintaining an optimal balance among its multiple key performance parameters. Simulation results demonstrate that within the relatively low intermediate frequency (IF) range of 2.7–3.3 GHz, this receiver front-end has an equivalent 20-dB shape factor (${\mathrm{SF}}_{20}$) of less than 2.14, which exhibits excellent selectivity. Consequently, it can efficiently suppress various interference signals, featuring an image-rejection ratio (IRR) exceeding 63 dB and a local-oscillator feedthrough rejection ratio (LOFTRR) surpassing 58 dB. Furthermore, this receiver front-end achieves a noise figure (NF) of less than 2.8 dB, a peak conversion gain (CG) ranging from 23.5 to 26.5 dB, and an input 1-dB compression point (IP1dB) greater than −23 dBm.