Liping Huang, Weiwei Fan, Chengtao Feng, Han Bao, Ning Wang, Quan Xu
{"title":"Initial-boosted dynamics in a memristive Chialvo map and its application for image encryption with hardware implementation","authors":"Liping Huang, Weiwei Fan, Chengtao Feng, Han Bao, Ning Wang, Quan Xu","doi":"10.1016/j.aeue.2024.155597","DOIUrl":null,"url":null,"abstract":"<div><div>Generally speaking, the discrete map possesses a low dimension and complex dynamics that can trigger hyperchaos to apply in image encryption. In this paper, we lead a memristor possessing cosine mem-conductance into the one-dimensional (1D) Chialvo map by sinusoidal-modulation-input method, thereby a two-dimensional (2D) memristive Chialvo (m-Chialvo) map is constructed. The fixed points stability and the forming mechanism for initial-boosted behavior are theoretically deduced. Numerical simulations show that the 2D m-Chialvo map can trigger initial-boosted hyperchaotic attractors, which hold the availability for image encryption. Besides, an FPGA-based digital platform is implemented to offer the verification of the initial-boosted hyperchaotic attractors. Furthermore, an STM32-based image encryption algorithm with hardware implementation is designed by deploying the coexisting hyperchaotic sequences, and the encrypted images can pass various performance tests. This verifies the feasibility of the hyperchaotic sequences for the algorithm in STM32-based image encryption with hardware implementation.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"189 ","pages":"Article 155597"},"PeriodicalIF":3.0000,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Aeu-International Journal of Electronics and Communications","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1434841124004837","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Generally speaking, the discrete map possesses a low dimension and complex dynamics that can trigger hyperchaos to apply in image encryption. In this paper, we lead a memristor possessing cosine mem-conductance into the one-dimensional (1D) Chialvo map by sinusoidal-modulation-input method, thereby a two-dimensional (2D) memristive Chialvo (m-Chialvo) map is constructed. The fixed points stability and the forming mechanism for initial-boosted behavior are theoretically deduced. Numerical simulations show that the 2D m-Chialvo map can trigger initial-boosted hyperchaotic attractors, which hold the availability for image encryption. Besides, an FPGA-based digital platform is implemented to offer the verification of the initial-boosted hyperchaotic attractors. Furthermore, an STM32-based image encryption algorithm with hardware implementation is designed by deploying the coexisting hyperchaotic sequences, and the encrypted images can pass various performance tests. This verifies the feasibility of the hyperchaotic sequences for the algorithm in STM32-based image encryption with hardware implementation.
期刊介绍:
AEÜ is an international scientific journal which publishes both original works and invited tutorials. The journal''s scope covers all aspects of theory and design of circuits, systems and devices for electronics, signal processing, and communication, including:
signal and system theory, digital signal processing
network theory and circuit design
information theory, communication theory and techniques, modulation, source and channel coding
switching theory and techniques, communication protocols
optical communications
microwave theory and techniques, radar, sonar
antennas, wave propagation
AEÜ publishes full papers and letters with very short turn around time but a high standard review process. Review cycles are typically finished within twelve weeks by application of modern electronic communication facilities.