{"title":"FPGA design and implementation of TRNG architecture using ADPLL based on fir as loop filter","authors":"Huirem Bharat Meitei, Manoj Kumar","doi":"10.1007/s10470-024-02295-8","DOIUrl":null,"url":null,"abstract":"<div><p>This article presents a comprehensive examination of the design, implementation, as well as analysis of a true random number generator (TRNG). The TRNG utilizes an all-digital phase-locked loop (ADPLL) that incorporates a finite impulse response (FIR) filter as the digital loop filter. The TRNG is implemented on the Artix 7 (XC7A35T-CPG236-1) FPGA board, leveraging the Xilinx Vivado v.2015.2 design suite. The computation of the coefficients for a third-order broadcast low pass digital FIR filter is performed via the Keiser window technique. The MATLAB filter design and analysis tool is utilized for the computation of filter coefficients. Following the application of the XOR-corrector post-processing method to mitigate bias in the sequence, the proposed designs of ADPLL-based TRNGs successfully generated an unbiased stochastic random number. These designs achieved an overall throughput of 200 Mbps for both configurations. The initial proposed design for a TRNG based on a Finite Impulse response-all-digital phase-locked loop (FIR-ADPLL), referred to as FAT-1, exhibits a power consumption of 0.072 W. In contrast, the subsequent proposed TRNG design, also based on a FIR-ADPLL, known as FAT-2, demonstrates a slightly higher power consumption of 0.074 W. The bitstream that is obtained is assessed for randomness through the application of the NIST test, which is conducted after post-processing. The Artrix-7 field-programmable gate array board is utilized to establish a connection with the DSO for the purpose of capturing the waveforms produced by the TRNG. Both of the suggested designs for FIR-based all-digital phase-locked loop true random number generators successfully underwent testing according to the NIST SP 800-22 standard. This indicates that these designs exhibit strong compatibility with a wide range of industrial applications, such as network security, cybersecurity, banking security, smart cards, RFID tags, the internet of things, and industrial internet of things.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"122 1","pages":""},"PeriodicalIF":1.2000,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-024-02295-8","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents a comprehensive examination of the design, implementation, as well as analysis of a true random number generator (TRNG). The TRNG utilizes an all-digital phase-locked loop (ADPLL) that incorporates a finite impulse response (FIR) filter as the digital loop filter. The TRNG is implemented on the Artix 7 (XC7A35T-CPG236-1) FPGA board, leveraging the Xilinx Vivado v.2015.2 design suite. The computation of the coefficients for a third-order broadcast low pass digital FIR filter is performed via the Keiser window technique. The MATLAB filter design and analysis tool is utilized for the computation of filter coefficients. Following the application of the XOR-corrector post-processing method to mitigate bias in the sequence, the proposed designs of ADPLL-based TRNGs successfully generated an unbiased stochastic random number. These designs achieved an overall throughput of 200 Mbps for both configurations. The initial proposed design for a TRNG based on a Finite Impulse response-all-digital phase-locked loop (FIR-ADPLL), referred to as FAT-1, exhibits a power consumption of 0.072 W. In contrast, the subsequent proposed TRNG design, also based on a FIR-ADPLL, known as FAT-2, demonstrates a slightly higher power consumption of 0.074 W. The bitstream that is obtained is assessed for randomness through the application of the NIST test, which is conducted after post-processing. The Artrix-7 field-programmable gate array board is utilized to establish a connection with the DSO for the purpose of capturing the waveforms produced by the TRNG. Both of the suggested designs for FIR-based all-digital phase-locked loop true random number generators successfully underwent testing according to the NIST SP 800-22 standard. This indicates that these designs exhibit strong compatibility with a wide range of industrial applications, such as network security, cybersecurity, banking security, smart cards, RFID tags, the internet of things, and industrial internet of things.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.