An improved SiC SWITCH-MOS with superior forward performance

IF 1.7 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IET Power Electronics Pub Date : 2024-11-01 DOI:10.1049/pel2.12808

Junji Cheng, Tao Zhong, Huan Li, Ping Li, Bo Yi, Haimeng Huang, Siliang Wang, Qiang Hu, Hongqiang Yang

{"title":"An improved SiC SWITCH-MOS with superior forward performance","authors":"Junji Cheng, Tao Zhong, Huan Li, Ping Li, Bo Yi, Haimeng Huang, Siliang Wang, Qiang Hu, Hongqiang Yang","doi":"10.1049/pel2.12808","DOIUrl":null,"url":null,"abstract":"An improved 4H-SiC SBD-wall-integrated trench metal-oxide-semiconductor (SWITCH-MOS) with n-bury and split-gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n-bury layer can smooth the path to current conduction, which reduces the specific on-resistance (RON, SP) and improves static characteristics. Besides, the split-gate is able to transform the gate-drain capacitance (CGD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH-MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH-MOS with almost the same BV, the proposed one reduces the RON, SP by 57% and the CGD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only −1.78 V, but its figure of merit reaches 1.67 GW/cm2 and 65 mΩ·nC, which is attractive for the application in power inverters.","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"17 15","pages":"2584-2590"},"PeriodicalIF":1.7000,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.12808","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Power Electronics","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/pel2.12808","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

An improved 4H-SiC SBD-wall-integrated trench metal-oxide-semiconductor (SWITCH-MOS) with n-bury and split-gate is proposed. Under the premise of ensuring breakdown voltage (BV), the n-bury layer can smooth the path to current conduction, which reduces the specific on-resistance (R_{ON, SP}) and improves static characteristics. Besides, the split-gate is able to transform the gate-drain capacitance (C_GD) and improve the dynamic characteristics. Therefore, a superior forward performance that SWITCH-MOS always craves is achieved. According to the simulation results, compared to the conventional SWITCH-MOS with almost the same BV, the proposed one reduces the R_{ON, SP} by 57% and the C_GD by 59% while gaining equally advanced reverse performance. Its reverse conduction voltage is only −1.78 V, but its figure of merit reaches 1.67 GW/cm² and 65 mΩ·nC, which is attractive for the application in power inverters.

Abstract Image

查看原文本刊更多论文

具有卓越正向性能的改进型 SiC SWITCH-MOS

本文提出了一种改进型 4H-SiC SBD 壁集成沟槽金属氧化物半导体（SWITCH-MOS），具有 n-bury 层和分裂栅极。在保证击穿电压（BV）的前提下，n-bury 层可以使电流传导路径更加顺畅，从而降低比导通电阻（RON，SP）并改善静态特性。此外，分裂栅还能改变栅漏电容（CGD），改善动态特性。因此，SWITCH-MOS 始终渴望的卓越正向性能得以实现。根据仿真结果，与具有几乎相同 BV 的传统 SWITCH-MOS 相比，所提出的 SWITCH-MOS 将 RON、SP 降低了 57%，CGD 降低了 59%，同时获得了同样先进的反向性能。它的反向传导电压仅为 -1.78 V，但优越性能却达到了 1.67 GW/cm2、65 mΩ-nC，这对于在功率变频器中的应用很有吸引力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IET Power Electronics ENGINEERING, ELECTRICAL & ELECTRONIC-

CiteScore

5.50

自引率

10.00%

发文量

195

审稿时长

5.1 months

期刊介绍： IET Power Electronics aims to attract original research papers, short communications, review articles and power electronics related educational studies. The scope covers applications and technologies in the field of power electronics with special focus on cost-effective, efficient, power dense, environmental friendly and robust solutions, which includes: Applications: Electric drives/generators, renewable energy, industrial and consumable applications (including lighting, welding, heating, sub-sea applications, drilling and others), medical and military apparatus, utility applications, transport and space application, energy harvesting, telecommunications, energy storage management systems, home appliances. Technologies: Circuits: all type of converter topologies for low and high power applications including but not limited to: inverter, rectifier, dc/dc converter, power supplies, UPS, ac/ac converter, resonant converter, high frequency converter, hybrid converter, multilevel converter, power factor correction circuits and other advanced topologies. Components and Materials: switching devices and their control, inductors, sensors, transformers, capacitors, resistors, thermal management, filters, fuses and protection elements and other novel low-cost efficient components/materials. Control: techniques for controlling, analysing, modelling and/or simulation of power electronics circuits and complete power electronics systems. Design/Manufacturing/Testing: new multi-domain modelling, assembling and packaging technologies, advanced testing techniques. Environmental Impact: Electromagnetic Interference (EMI) reduction techniques, Electromagnetic Compatibility (EMC), limiting acoustic noise and vibration, recycling techniques, use of non-rare material. Education: teaching methods, programme and course design, use of technology in power electronics teaching, virtual laboratory and e-learning and fields within the scope of interest. Special Issues. Current Call for papers: Harmonic Mitigation Techniques and Grid Robustness in Power Electronic-Based Power Systems - https://digital-library.theiet.org/files/IET_PEL_CFP_HMTGRPEPS.pdf