Dual-Layer Thin-Film Transistor Analysis and Design

Abstract

A set of analytical equations is formulated for the analysis and design of a dual-layer thin-film transistor (TFT). For a given TFT structure, in which each channel layer thickness is specified, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. In order to implement this EKV-based equation, only one model parameter function is required, i.e., drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the dual-layer TFT. In order to use the model, ten semiconductor physical properties must be specified, five for each semiconductor channel layer; namely, low-frequency (static) relative dielectric constant, free electron concentration, maximum (no trapping) mobility, and slope & intercept parameters characterizing the semiconductor trap density. Additionally, model implementation requires knowing two structure properties (insulator capacitance density and TFT width-to-length ratio), and one physical operating parameter (temperature). Simulation of dual-layer TFTs reveals that optimal mobility performance is obtained when the higher mobility semiconductor is positioned as the bottom channel layer, while the lower mobility semiconductor top channel layer is made as thin as is practicable.