Miao Zhu, Xuexia Yang, Yanxi Sun, Ze Wang, Erqiang Liu
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引用次数: 0
Abstract
The packaging of chip-scale (CSP) devices plays a pivotal role in enhancing the reliability of CSP under thermal cycling conditions, largely due to the intricate structure and the recurrent alterations in the actual operating environment. The objective of this study is to enhance the reliability of solder joints by optimising the structural parameters of CSP packaging in order to reduce the strain values at the solder joints. In order to enhance the design efficiency and accuracy of the computational model, the Anand model is adopted in order to define the solder joint parameters, and finite element simulations are conducted using Ansys software. This paper puts forward a novel intelligent algorithm that fuses response surface methodology with a neural network-particle swarm optimization algorithm, thereby enhancing the precision of the system. The method is capable of identifying the combination with the minimum strain value using limited data, thereby addressing the issue of insufficient generalisation ability in conventional methods. The implementation of this method into the model resulted in a minimum strain value of 4.071 × 10−3, representing a 37.6 % reduction compared to the original CSP structure. Furthermore, the optimized lifespan is approximately 3.24 times longer than that observed prior to optimization. The approach presented in this paper has the potential to significantly enhance design efficiency and increase the lifespan of components. It offers a novel perspective for optimising the structural parameters of CSP packaging.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.