Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network

Abstract

With the rapid development of artificial intelligence technology, in-memory computing has become a research hotspot. In this article, we propose an in-memory computing (IMC) architecture that achieves high energy efficiency and performance. Our work is based on the working mechanism of charge sharing, enabling configurable multi-bit Multiply-Accumulate operations. This work employs a unique bit-cell structure to implement sparse strategies at the bit-level in IMC arrays and compensates for errors caused by non-ideal effects, thus achieving better energy efficiency and performance. A hardware-aware quantification method and a hardware simulation model based on Pytorch have been proposed to evaluate the hardware mapping and compare with other charge domain IMC works. The MNIST and CIFAR-10 datasets have been used to validate algorithm models and chip performance, achieving accuracy rates of 97.6% and 90.5% respectively. The IMC chip was fabricated with a 180 nm CMOS process. The measurement shows that the chip achieves an energy efficiency of 41.8 TOPS/W.