Linearity analysis of FE-based graded channel junctionless FET obtaining negative capacitance for low power applications

Abstract

This paper reports ferroelectric (FE) oxide based graded-channel junctionless FET featuring the negative capacitance effects in nano-scale regime. The linearity nature of its response is analyzed on the basis of third order interception point ($P_{IP3}$), harmonic interception voltages of 2nd and 3rd orders ($VI{P}_2$, $VI{P}_3$) and intermodulation distortion ($IM{D}_3$). Influence of fundamental device’s parameters such as, gate and underlap length, ferroelectric oxide thickness, graded channel doping and operating temperature on its linear behavior is observed and analyzed in detail. The subthreshold slope is also found to go below 60mV/dec for optimum features, obtaining the NC characteristics. In its circuit application part, a cascode amplifier is designed using the proposed device showing variations due to the change in the proposed device dimensions. The proposed device is designed and simulated using Silvaco ATLAS device simulator, which is calibrated with the available experimental results. Therefore, the present study is quite relevant in recent days for low power analog applications.